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CS61305A
T1/E1 Line Interface
Features General Description
The CS61305A combines the complete analog transmit and receive line interface for T1 or E1 applications in a low power, 28-pin device operating from a +5V supply. The CS61305A is a pin-compatible replacement for the LXT305A in most applications. The CS61305A provides a transmitter jitter attenuator making it ideal for use in asynchronous multiplexor systems with gapped transmit clocks. The transmitter features internal pulse shaping and a low impedance output stage allowing the use of external resistors for transmitter impedance matching. The receiver uses a digital Delay-Locked-Loop clock and data recovery circuit which is continuously calibrated from a crystal reference to provide excellent stability and jitter tolerance.
*
Provides Analog Transmission Line Interface for T1 and E1 Applications
Jitter Attenuator * Provides Line Driver,Functions and Clock Recovery Side Jitter * Transmitat 3 Hz, withAttenuationof Jitter Starting > 300 UI Tolerance
* B8ZS/HDB3/AMI Encoders/Decoders with * Compatible OtherSONET, M13 , CCITT G.742, and Asynchronous Muxes * 50 mA Transmitter Short-Circuit Current Limiting
Applications
* *
Interfacing network transmission equipment such as SONET multiplexor and M13 to a DSX-1 cross connect. Interfacing customer premises equipment to a CSU.
ORDERING INFORMATION CS61305A-IP1 28 Pin Plastic DIP CS61305A-IL1 28 Pin Plastic PLCC
[ ] = Pin Function in Extended Hardware Mode ( ) = Pin Function in Host Mode XTALIN XTALOUT
9 10
(CLKE) (INT) (SDI) (SDO) MODE TAOS LEN0 LEN1 LEN2
5 28 23 24 25
TGND
14
TV+
15
TCLK TPOS [TDATA] TNEG [TCODE] RCLK RPOS [RDATA] RNEG [BPV]
2 3 4 8 7 6 LOOP BACK AMI, B8ZS, HDB3 CODER
13
JITTER ATTENUATOR
CONTROL
TTIP
PULSE SHAPER
CLOCK & DATA RECOVERY
16 TRING LINE DRIVER LINE RECEIVER 19 RTIP
20 RRING
SIGNAL QUALITY MONITOR 26 1 12 21 22
DRIVER MONITOR
27
17 MTIP [RCODE] 18 MRING [PCS] 11 DPM [AIS]
LLOOP RLOOP (SCLK) (CS)
ACLKI LOS
RV+ RGND
Preliminary Product Information
Crystal Semiconductor Corporation P. O. Box 17847, Austin, Texas, 78760 (512) 445 7222 FAX:(512) 445 7581
This document contains information for a new product. Crystal Semiconductor reserves the right to modify this product without notice.
Copyright (c) Crystal Semiconductor Corporation 1996 (All Rights Reserved)
MAY '96 DS157PP3 1
CS61305A
ABSOLUTE MAXIMUM RATINGS
Parameter DC Supply (referenced to RGND=TGND=0V) Symbol Min Max Units RV+ 6.0 V TV+ (RV+) + 0.3 V Input Voltage, Any Pin (Note 1) Vin RGND-0.3 (RV+) + 0.3 V Input Current, Any Pin (Note 2) Iin -10 10 mA Ambient Operating Temperature TA -40 85 C Storage Temperature Tstg -65 150 C WARNING:Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V. 2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND can withstand a continuous current of 100 mA.
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Units DC Supply (Note 3) RV+, TV+ 4.75 5.0 5.25 V Ambient Operating Temperature TA -40 25 85 C Power Consumption (Notes 4,5) PC 350 mW Notes: 3. TV+ must not exceed RV+ by more than 0.3V. 4. Power consumption while driving line load over operating temperature range. Includes IC and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 5. Assumes 100% ones density and maximum line length at 5.25V.
DIGITAL CHARACTERISTICS
Parameter
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V) Symbol Min Typ Max Units V V V V A V V V
High-Level Input Voltage (Notes 6, 7) VIH 2.0 PINS 1-4, 17, 18, 23-28 Low-Level Input Voltage (Notes 6, 7) VIL 0.8 PINS 1-4, 17, 18, 23-28 High-Level Output Voltage (Notes 6, 7, 8) VOH 2.4 IOUT = -400 A PINS 6-8, 11, 12, 25 Low-Level Output Voltage (Notes 6, 7, 8) VOL 0.4 IOUT = 1.6 mA PINS 6-8, 11, 12, 23, 25 Input Leakage Current (Except Pin 5) 10 Low-Level Input Voltage, PIN 5 VIL 0.2 High-Level Input Voltage, PIN 5 VIH (RV+) - 0.2 Mid-Level Input Voltage, PIN 5 (Note 9) VIM 2.3 2.7 Notes: 6. In Extended Hardware Mode, pins 17 and 18 are digital inputs. In Host Mode, pin 23 is an open drain output and pin 25 is a tristate digital output. 7. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40A). 8. Output drivers will drive CMOS logic levels into a CMOS load. 9. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating.
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DS157PP3
CS61305A
ANALOG SPECIFICATIONS
Parameter
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V) Min Typ Max Units
Transmitter AMI Output Pulse Amplitudes (Note 10) 2.14 2.37 2.6 V E1, 75 (Note 11) 2.7 3.0 3.3 V E1, 120 (Note 12) 2.7 3.0 3.3 V T1, FCC Part 68 (Note 13) 2.4 3.0 3.6 V T1, DSX-1 (Note 14) E1 Zero (space) level (LEN2/1/0 = 000) -0.237 0.237 V 1:1 transformer and 75 load -0.3 0.3 V 1:1.26 transformer and 120 load Load Presented To Transmitter Output (Note 10) 75 Jitter Added by the Transmitter (Note 15) 10Hz - 8kHz 0.01 UI 8kHz - 40kHz 0.025 UI 10Hz - 40kHz 0.025 UI 0.05 UI Broad Band Power in 2kHz band about 772kHz (Notes 10, 16) 12.6 15 17.9 dBm Power in 2kHz band about 1.544MHz (Notes 10, 16) -29 -38 dB (referenced to power in 2kHz band at 772kHz) Positive to Negative Pulse Imbalance (Notes 10, 16) T1, DSX-1 0.2 0.5 dB E1 amplitude at center of pulse -5 5 % -5 5 % E1 pulse width at 50% of nominal amplitude E1 Transmitter Return Loss (Notes 10, 16, 17) 51 kHz to 102 kHz 20 28 dB 102 kHz to 2.048 MHz 20 28 dB 20 24 dB 2.048 MHz to 3.072 MHz E1 Transmitter Short Circuit Current (Notes 10, 18) 50 mA RMS Notes: 10. Using a 0.47 F capacitor in series with the primary of a transformer recommended in the Applications Section. 11. Pulse amplitude measured at the output of a 1:1 transformer across a 75 load for line length setting LEN2/1/0 = 0/0/0. 12. Pulse amplitude measured at the output of a 1:1.26 transformer across a 120 load for line length setting LEN2/1/0 = 0/0/0 or at the output of a 1:1 transformer across a 120 load for LEN2/1/0 = 001. 13. Pulse amplitude measured at the output of a 1:1.15 transformer across a 100 load for line length setting LEN2/1/0 = 0/1/0. 14. Pulse amplitude measured at the DSX-1 Cross-Connect across a 100 load for all line length settings from LEN2/1/0 = 0/1/1 to LEN2/1/0 = 1/1/1 using a 1:1.5 transformer. 15. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK. 16. Not production tested. Parameters guaranteed by design and characterization. 17. Return loss = 20 log10 ABS((z1 +z0)/(z1-z0)) where z1 = impedance of the transmitter, and z0 = impedance of line load. Measured with a repeating 1010 data pattern with LEN2/1/0 = 0/0/0 and a 1:2 transformer with two 9.4 series resistors terminated by a 75 load, or for LEN2/1/0 = 0/0/1 with a 1:2 transformer and two 15 series resistors terminated by a 120 load. 18. Measured broadband through a 0.5 resistor across the secondary of the transmitter transformer during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0 or 0/0/1with a 1:2 transformer and the series resistors specified in Table A1.
DS157PP3
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CS61305A
ANALOG SPECIFICATIONS
Parameter
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V) Min (Notes 16, 19) (Notes 16, 19) (Notes 16, 19) Protection) 138 Typ 3 50 Max Units Hz dB UI
Transmitter Jitter Attenuator Jitter Attenuation Curve Corner Frequency Attenuation at 10kHz Jitter Frequency Attenuator Input Jitter Tolerance (Before Onset of FIFO Overflow or Underflow Receiver RTIP/RRING Input Impedance Sensitivity Below DSX (0dB = 2.4V)
-13.6 500
50k -
-
dB mV
Data Decision Threshold T1, DSX-1 (Note 20) 53 65 77 % of peak T1, (FCC Part 68) and E1 (Note 21) 45 50 55 % of peak Allowable Consecutive Zeros before LOS 160 175 190 bits Receiver Input Jitter Tolerance (Note 22) 10kHz - 100kHz 0.4 UI 6.0 UI 2kHz 300 UI 10Hz and below Loss of Signal Threshold 0.30 V Notes: 19. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates jitter at 20 dB/decade above the corner frequency. See Figure 10. Output jitter can increase significantly when more than 12 UI's are input to the attenuator. See discussion in the text section. 20. For input amplitude of 1.2 Vpk to 4.14 Vpk. 21. For input amplitude of 1.05 Vpk to 3.3 Vpk. 22. Jitter tolerance increases at lower frequencies. See Figure 12.
E1 SWITCHING CHARACTERISTICS
Parameter Crystal Frequency ACLKI Duty Cycle ACLKI Frequency RCLK Cycle Width
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Symbol (Note 23) (Note 24) (Note 25) fc tpwh3/tpw3 faclki tpw1 tpwh1 tpwl1 tr tf ftclk tpwh2 tsu2 th2 tsu1 tsu1 tsu1 th1 th1 th1 Min 40 310 90 120 80 150 25 25 100 100 100 100 100 100 Typ 8.192000 2.048 488 140 348 2.048 194 194 194 194 194 194 Max 60 620 190 500 85 85 340 Units MHz % MHz ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns
Rise Time, All Digital Outputs Fall Time, All Digital Outputs TCLK Frequency TCLK Pulse Width
(Note 26) (Note 26) 28) 30)
(Notes 27, (Notes 29, TPOS/TNEG (TDATA) to TCLK Falling Setup Time TCLK Falling to TPOS/TNEG (TDATA) Hold Time RPOS/RNEG Valid Before RCLK Falling (Note RDATA Valid Before RCLK Falling (Note RPOS/RNEG Valid Before RCLK Rising (Note RPOS/RNEG Valid After RCLK Falling (Note RDATA Valid After RCLK Falling (Note RPOS/RNEG Valid After RCLK Rising (Note
27) 29) 28) 27) 29) 28)
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DS157PP3
CS61305A
T1 SWITCHING CHARACTERISTICS
Parameter Crystal Frequency ACLKI Duty Cycle ACLKI Frequency RCLK Cycle Width
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Symbol (Note 23) fc tpwh3/tpw3 faclki tpw1 tpwh1 tpwl1 tr tf ftclk tpwh2 Min Typ Max Units
6.176000 MHz 40 60 % (Note 24) 1.544 MHz (Note 25) 320 648 980 ns 130 190 240 ns 100 458 850 ns 85 ns Rise Time, All Digital Outputs (Note 26) Fall Time, All Digital Outputs (Note 26) 85 ns TCLK Frequency 1.544 MHz TCLK Pulse Width (Notes 16, 27, 28) 80 ns (Notes 29, 30) 150 500 ns TPOS/TNEG (TDATA) to TCLK Falling Setup Time tsu2 25 ns TCLK Falling to TPOS/TNEG (TDATA) Hold Time th2 25 ns RPOS/RNEG Valid Before RCLK Falling (Note 27) tsu1 150 274 ns RDATA Valid Before RCLK Falling (Note 29) tsu1 150 274 ns RPOS/RNEG Valid Before RCLK Rising (Note 28) tsu1 150 274 ns RPOS/RNEG Valid After RCLK Falling (Note 27) th1 150 274 ns RDATA Valid After RCLK Falling (Note 29) th1 150 274 ns RPOS/RNEG Valid After RCLK Rising (Note 28) th1 150 274 ns Notes: 23. Crystal must meet specifications described in CXT6176/CXT8192 data sheet. 24. ACLKI provided by an external source or TCLK but not RCLK. 25. RCLK duty cycle will vary with extent by which pulses are displaced by jitter. Specified under worst case jitter conditions: 0.4 UI AMI data displacement for T1 and 0.2 UI AMI data displacement for E1. 26. At max load of 1.6 mA and 50 pF. 27. Host Mode (CLKE = 1). 28. Hardware Mode, or Host Mode (CLKE = 0). 29. Extended Hardware Mode. 30. The maximum TCLK burst rate is 5 MHz and tpw2 (min) = 200ns. The maximum gap size that can be tolerated on TCLK is 138 VI.
DS157PP3
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CS61305A
SWITCHING CHARACTERISTICS
Inputs: Logic 0 = 0V, Logic 1 = RV+) Parameter SDI to SCLK Setup Time SCLK to SDI Hold Time SCLK Low Time SCLK High Time SCLK Rise and Fall Time CS to SCLK Setup Time SCLK to CS Hold Time CS Inactive Time SCLK to SDO Valid CS to SDO High Z Input Valid To PCS Falling Setup Time PCS Rising to Input Invalid Hold Time PCS Active Low Time Notes: 31. Output load capacitance = 50pF.
(TA = -40 to 85C; TV+, RV+ = 5%; Symbol tdc tcdh tcl tch tr, tf tcc tcch tcwh tcdv tcdz tsu4 th4 tpcsl Min 50 50 240 240 50 50 250 50 50 250 Typ 100 Max 50 200 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
(Note 31)
tr 90% 10% 90%
tf
Any Digital Output
10%
Figure 1. Signal Rise and Fall Characteristics
tpw1
RCLK
t pwl1
t su1
t pwh1
t h1
EXTENDED HARDWARE MODE OR HOST MODE (CLKE = 1)
RPOS RNEG RDATA BPV
RCLK
HARDWARE MODE OR HOST MODE (CLKE = 0)
Figure 2. Recovered Clock and Data Switching Characteristics
6
DS157PP3
CS61305A
t pw2 t pwh2
TCLK
t su2 TPOS/TNEG
Figure 3a. Transmit Clock and Data Switching Characteristics
t pw3
t h2 ACLKI
t pwh3
Figure 3b. Alternate External Clock Characteristics
t cwh
CS t cc SCLK t dc SDI LSB CONTROL BYTE t cdh LSB DATA BYTE t cdh MSB t ch t cl t cch
Figure 4. Serial Port Write Timing Diagram
CS t cdz SCLK t cdv SDO CLKE = 1 HIGH Z
Figure 5. Serial Port Read Timing Diagram
PCS t su4 LEN0/1/2, TAOS, RLOOP, LLOOP, RCODE, TCODE t pcsl
VALID INPUT DATA
th4
Figure 6. Extended Hardware Mode Parallel Chip Select Timing Diagram
DS157PP3
7
CS61305A
THEORY OF OPERATION Key Enhancements of the CS61305A Relative to the LXT305A * * * * * 12.5% lower power consumption, 50 mARMS transmitter short-circuit current limiting for E1 (per OFTEL OTR-001), Optional AMI, B8ZS, HDB3 encoder/decoder or external line coding support, Receiver AIS (unframed all ones) detection, Improved receiver Loss of Signal handling (LOS set at power-up, reset upon receipt of 3 ones in 32 bit periods with no more than 15 consecutive zeros), Transmitter TTIP and TRING outputs are forced low when TCLK is static.
Control Method MODE Pin Level Line Coding AIS Detection Driver Performance Monitor
Hardware Mode Control Pins <0.2 V
Extended Host Hardware Mode Mode Control Pins Serial with Parallel Interface Chip Select Floating or >(RV+)-0.2 2.5 V V InternalAMI, B8ZS, or HDB3 Yes No External
External
No Yes
No Yes
*
Table 1. Differences Between Operating Modes
Introduction to Operating Modes The CS61305A supports three operating modes which are selected by the level of the MODE pin as shown in Tables 1 and 2, Figure 7, and Figures A1-A3 of the Applications section. There are thirteen multi-function pins whose functionality is determined by the operating mode. (see Table 2). The modes are Hardware Mode, Extended Hardware Mode, and Host Mode. In Hardware and Extended Hardware Modes, discrete pins are used to configure and monitor the device. The Extended Hardware Mode provides a parallel chip select input which latches the control inputs allowing individual ICs to be configured using a common set of control lines. In the Host Mode, an external processor monitors and configures the device through a serial interface.
MODE EXTENDED FUNCTION PIN HARDWARE HARDWARE 3 TPOS TDATA TRANSMITTER TCODE 4 TNEG 6 RNEG BPV 7 RPOS RDATA RECEIVER/DPM 11 DPM AIS RCODE 17 MTIP 18 MRING PCS 18 23 LEN0 LEN0 24 LEN1 LEN1 CONTROL 25 LEN2 LEN2 26 RLOOP RLOOP 27 LLOOP LLOOP 28 TAOS TAOS
HOST TPOS TNEG RNEG RPOS DPM MTIP MRING INT SDI SDO CS SCLK CLKE
Table 2. Pin Definitions
8
DS157PP3
CS61305A
HARDWARE MODE
TAOS LLOOP RLOOP LEN0/1/2
CONTROL TPOS
TNEG
JITTER ATTENUATOR
TTIP LINE DRIVER
MRING MTIP TRING
TRANSMIT TRANSFORMER
CS62180B FRAMER CIRCUIT
CS61305A
RPOS RNEG
DRIVER MONITOR
DPM RTIP LINE RECEIVER
RRING
RECEIVE TRANSFORMER
EXTENDED HARDWARE MODE
TCODE RCODE TAOS LLOOP RLOOP PCS LEN0/1/2
CONTROL TTIP TDATA AMI B8ZS, HDB3, CODER RDATA JITTER ATTENUATOR LINE DRIVER TRING TRANSMIT TRANSFORMER
HIGH SPEED MUX (e.g., M13)
CS61305A
RTIP AIS DETECT LINE RECEIVER
RRING
RECEIVE TRANSFORMER
BPV P SERIAL PORT 5
AIS
HOST MODE
CLKE
CONTROL TPOS TNEG CS62180B FRAMER CIRCUIT RPOS RNEG
CONTROL TTIP JITTER ATTENUATOR LINE DRIVER
MRING MTIP
TRING
TRANSMIT TRANSFORMER
CS61305A
DRIVER MONITOR
DPM RTIP
LINE RECEIVER
RRING
RECEIVE TRANSFORMER
Figure 7. Overview of Operating Modes DS157PP3 9
CS61305A
Transmitter The transmitter takes digital T1 or E1 input data and drives appropriately shaped bipolar pulses onto a transmission line. The transmit data (TPOS & TNEG or TDATA) is supplied synchronously and sampled on the falling edge of the input clock, TCLK. Either T1 (DSX-1 or Network Interface) or E1 CCITT G.703 pulse shapes may be selected. Pulse shaping and signal level are controlled by "line length select" inputs as shown in Table 3. The output options in Table 3 are specified with a 1:1.15 transmitter transformer turns ratio for T1 and a 1:1 turns ratio for E1 without external series resistors. Other turns ratios may be used if approriate resistors are placed in series with the TTIP and TRING pins. Table A1 in the applications section lists other combinations which can be used to provide transmitter impedance matching. For T1 DSX-1 applications, line lengths from 0 to 655 feet (as measured from the transmitter to the DSX-1 cross connect) may be selected. The five partition arrangement in Table 3 meets ANSI T1.102-1993 and AT&T CB-119 requirements when using #22 ABAM cable. A typical output pulse is shown in Figure 8. These pulse settings can also be used to meet CCITT pulse shape requirements for 1.544 MHz operation. For T1 Network Interface applications, two additional options are provided. Note that the optimal pulse width for Part 68 (324 ns) is narrower than the optimal pulse width for DSX-1 (350 ns). The CS61305A automatically adjusts the pulse width based upon the "line length" selection made. The E1 G.703 pulse shape is supported with line length selections LEN2/1/0 = 0/0/0 and 0/0/1. The pulse width will meet the G.703 pulse shape template shown in Figure 9, and specified in Table 4.
10
LEN2 LEN1 LEN0 Option Selected Application 0 1 1 0-133 ft DSX-1 1 0 0 133-266 ft ABAM 1 0 1 266-399 ft (AT&T 600B 1 1 0 399-533 ft or 600C) 1 1 1 533-655 ft 0 0 0 E1 75 coax CCITT G.703 0 0 1 120 twisted-pair 0 1 0 FCC PART 68, OPT. A Network Interface 0 1 1 ANSI T1.403
Table 3. Line Length Selection
The CS61305A transmitter provides short-circuit current limiting protection and meets OFTEL OTR-001 short-circuit current limiting requirements for E1 applications. The CS61305A will detect a static TCLK, and will force TTIP and TRING low to prevent transmission when data is not present. When any transmit control pin (TAOS, LEN0-2 or LLOOP) is toggled, the transmitter outputs will require approximately 22 bit periods to stabilize. The transmitter will take longer to stabilize when RLOOP is selected because the timing circuitry must adjust to the new frequency.
NORMALIZED AMPLITUDE 1.0 ANSI T1.102, AT&T CB 119 SPECIFICATIONS
0.5
0 OUTPUT PULSE SHAPE -0.5 0 250 500 750 1000
TIME (nanoseconds)
Figure 8. Typical Pulse Shape at DSX-1 Cross Connect DS157PP3
CS61305A
Percent of nominal peak voltage 120 110 100 90 80 244 ns 194 ns
0
269 ns
a) Minimum Attenuation Limit 10 20 30 40 50 60 1 10 100 AT&T 62411 Requirements
Attenuation in dB
50
b) Maximum Attenuation Limit Measured Performance
10 0 -10 -20 219 ns 488 ns
Nominal Pulse
1k
10 k
Frequency in Hz
Figure 10. Typical Jitter Attenuation Curve
Figure 9. Mask of the Pulse at the 2048 kbps Interface
Transmit All Ones Select The transmitter provides for all ones insertion at the frequency of ACLKI. Transmit all ones is selected when TAOS goes high, and causes continuous ones to be transmitted on the line (TTIP and TRING). In this mode, the TPOS and TNEG (or TDATA) inputs are ignored. A TAOS request will be ignored if remote loopback is in effect. ACLKI jitter will be attenuated. TAOS is not available on the CS61305A when ACLKI is grounded.
Jitter Attenuator The jitter attenuator is designed to reduce wander and jitter in the transmit clock signal. It consists of a 192 bit FIFO, a crystal oscillator, a set of load capacitors for the crystal, and control logic. The jitter attenuator exceeds the jitter attenuation requirements of Publications 43802 and REC. G.742. A typical jitter attenuation curve is shown in Figure 10. The jitter attenuator works in the following manner. Data on TPOS and TNEG (or TDATA) are
Fo r c o ax i al c a bl e, For shielded twisted 75 load a nd pair, 120 load and transformer specified transformer specified in Application Section. in Application Section. 2.37 V 3V 0 0.237 V 0 0.30 V 244 ns
Nominal peak voltage of a mark (pulse) Peak voltage of a space (no pulse) Nominal pulse width Ratio of the amplitudes of positive and negative 0.95 to 1.05* pulses at the center of the pulse interval Ratio of the widths of positive and negative 0.95 to 1.05* pulses at the nominal half amplitude * When configured with a 0.47 F nonpolarized capacitor in series with the TX transformer primary as shown in Figures A1, A2 and A3. Table 4. CCITT G.703 Specifications DS157PP3
11
CS61305A
written into the jitter attenuator's FIFO by TCLK. The rate at which data is read out of the FIFO and transmitted is determined by the oscillator. Logic circuits adjust the capacitive loading on the crystal to set its oscillation frequency to the average of the TCLK frequency. Signal jitter is absorbed in the FIFO. Jitter Tolerance of Jitter Attenuator The FIFO in the jitter attenuator is designed to neither overflow nor underflow. If the jitter amplitude becomes very large, the read and write pointers may get very close together. Should the pointers attempt to cross, the oscillator's divide by four circuit adjusts by performing a divide by 3 1/2 or divide by 4 1/2 to prevent the overflow or underflow. When a divide by 3 1/2 or 4 1/2 occurs, the data bit will be driven on to the line either an eighth bit period early or an eighth bit period late. The FIFO of the jitter attenuator in the transmit path is 192 bits deep. This FIFO will typically be near the half full point under normal operating conditions, buffering about 96 bits of data. The number of bits actually buffered depends on the relationship of the nominal TCLK frequency to the center frequency of the crystal oscillator. As these frequencies deviate, a few bits of FIFO depth will be lost. TCLK can have gaps or bursts. As long as the gap or burst is less than the remaining FIFO depth, normal operation will continue. For example, if the nominal TCLK frequency was less than the oscillator's center frequency by 40 Hz. The FIFO will operate 3-4 bits off center or 92 bits full. A gap in TCLK of 80 cycles would empty the FIFO by 80 bits but would still not envoke the divide by 4 1/2 circuitry, as about 12 bits would remain in the FIFO. The crystal frequency must be 4 times the nominal signal frequency: 6.176 MHz for 1.544 MHz operation; 8.192 MHz for 2.048 MHz applica12
tions. Internal capacitors load the crystal, controlling the oscillation frequency. The crystal must be designed so that over operating temperature, the oscillator frequency range exceeds the system frequency tolerance. Crystal Semiconductor offers the CXT6176 & CXT8192 crystals, which yield optimum performance with the CS61305A. Receiver The receiver extracts data and clock from an AMI (Alternate Mark Inversion) coded signal and outputs clock and synchronized data. The receiver is sensitive to signals over the entire range of cable lengths and requires no equalization or ALBO (Automatic Line Build Out) circuits. The signal is received on both ends of a center-tapped, centergrounded transformer. The transformer is center-tapped on the IC side. The clock and data recovery circuit exceeds the jitter tolerance specifications of Publications 43802, 43801, 62411 amended, TR-TSY-000170, and CCITT REC. G.823. A block diagram of the receiver is shown in Figure 11. The two leads of the transformer (RTIP and RRING) have opposite polarity allowing the receiver to treat RTIP and RRING as unipolar signals. Comparators are used to detect pulses on RTIP and RRING. The comparator thresholds are dynamically established at a percent of the peak level (50% of peak for E1, 65% of peak for T1; with the slicing level selected by LEN2/1/0). The receiver uses an edge detector and a continuously calibrated delay line to generate the recovered clock. The delay line divides its reference clock, ACLKI or the jitter attenuator's oscillator, into 13 equal divisions or phases. Continuous calibration assures timing accuracy, even if temperature or power supply voltage fluctuate. The leading edge of an incoming data pulse triggers the clock phase selector. The phase selector chooses one of the 13 available phases which the delay line produces for each bit period. The outDS157PP3
CS61305A
1:2 RTIP
Data Level Slicer RRING
Data Sampling & Clock Extraction
RPOS RNEG
RCLK
Edge Detector
Clock Phase Selector
Continuously Calibrated Delay Line
ACLKI or Oscillator in Jitter Attenuator
Figure 11. Receiver Block Diagram
put from the phase selector feeds the clock and data recovery circuits which generate the recovered clock and sample the incoming signal at appropriate intervals to recover the data. The jitter tolerance of the receiver exceeds that shown in Figure 12. The CS61305A outputs a clock immediately upon power-up and will lock onto the AMI data input immediately. If loss of signal occurs, the RCLK frequency will equal the ACLKI frequency.
In the Hardware Mode, data at RPOS and RNEG is stable and may be sampled on the rising edge of the recovered clock. In the Extended Hardware Mode, data at RDATA is stable and may be sampled on the fallings edge of the recovered clock. In the Host Mode, CLKE determines the clock polarity for which output data is stable and valid as shown in Table 5. Jitter and Recovered Clock The CS61305A is designed for error free clock and data recovery from an AMI encoded data
MODE (pin 5) LOW (<0.2V) HIGH (>(V+) - 0.2V) HIGH (>(V+) - 0.2V) CLKE (pin 28) X LOW DATA RPOS RNEG RPOS RNEG SDO RPOS RNEG SDO RDATA CLOCK RCLK RCLK RCLK RCLK SCLK RCLK RCLK SCLK RCLK Clock Edge for Valid Data Rising Rising Rising Rising Falling Falling Falling Rising Falling
300 138 100 AT&T 62411 28 10 PEAK-TO-PEAK JITTER (unit intervals) 1 .4
Minimum Performance
HIGH
.1 1 10 100 300 700 1k JITTER FREQUENCY (Hz) 10k 100k
MIDDLE (2.5V)
X
X = Don't care
Figure 12. Minimum Input Jitter Tolerance of Receiver
Table 5. Data Output/Clock Relationship
DS157PP3
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CS61305A
stream in the presence of more than 0.4 unit intervals of jitter at high frequency. The clock recovery circuit is also tolerant of long strings of zeros. The edge of an incoming data bit causes the circuitry to choose a phase from the delay line which most closely corresponds with the arrival time of the data edge, and that clock phase triggers a pulse which is typically 140 ns in duration. This phase of the delay line will continue to be selected until a data bit arrives which is closer to another of the 13 phases, causing a new phase to be selected. The largest jump allowed along the delay line is six phases. When an input signal is jitter free, the phase selection will occasionally jump between two adjacent phases resulting in RCLK jitter with an amplitude of 1/13 UIpp. These single phase jumps are due to differences in frequency of the incoming data and the calibration clock input to ACLKI. For T1 operation the instantaneous period can be 14/13 * 648 ns = 698 ns or 12/13 * 648 ns = 598 ns when adjacent clock phases are chosen. As long as the same phase is chosen, the period will be 648 ns. Similar calculations hold for the E1 rate. The clock recovery circuit is designed to accept at least 0.4 UI of jitter at the receiver. Since the data stream contains information only when ones are transmitted, a clock/data recovery circuit must assume a zero when no signal is measured during a bit period. Likewise, when zeros are received, no information is present to update the clock recovery circuit regarding the trend of a signal which is jittered. The result is that two ones that are separated by a string of zeros can exhibit maximum deviation in pulse arrival time. For example, one half of a period of jitter at 100 kHz occurs in 5 s, which is 7.7 T1 bit periods. If the jitter amplitude is 0.4 UI, then a one preceded by seven zeros can have maximum displacement in arrival time, i.e. either 0.4 UI too early or 0.4 UI too late. The data recovery circuit correctly assigns a received bit to its proper clock period if it is displaced by
14
less than 6/13 of a bit period from its optimal location. Theoretically, this would give a jitter tolerance of 0.46 UI. The actual jitter tolerance of the CS61305A is only slightly less than the ideal. In the event of a maximum jitter hit, the RCLK clock period immediately adjusts to align itself with the incoming data and prepare to accurately place the next one, whether it arrives one period later, or after another string of zeros and is displaced by jitter. For a maximum early jitter hit, RCLK will have a period of 7/13 * 648 ns = 349 ns. For a maximum late jitter hit, RCLK will have a period of 19/13 * 648 ns = 947 ns. Loss of Signal Receiver loss of signal is indicated upon receiving 175 consecutive zeros. A digital counter counts received zeros based on RCLK cycles. A zero input is determined either when zeros are received, or when the received signal amplitude drops below a 0.3 V peak threshold. The receiver reports loss of signal by setting the Loss of Signal pin, LOS, high. If the serial interface is used, the LOS bit will be set and an interrupt issued on INT. LOS will go low (and flag the INT pin again if serial I/O is used) when a valid signal is detected. Note that in the Host Mode, LOS is simultaneously available from both the register and pin 12. In a loss of signal state, the RCLK frequency will be equal to the ACLKI frequency since ACLKI is being used to calibrate the clock recovery circuit. Received data is output on RPOS/RNEG regardless of LOS status. LOS returns to logic zero when 3 ones are received out of 32 bit periods containing no more than 15 consecutive zeros. Also, a power-up or manual reset will set LOS high.
DS157PP3
CS61305A
Local Loopback Local loopback is selected by taking LLOOP, pin 27, high or by setting the LLOOP register bit via the serial interface. The local loopback mode takes clock and data presented on TCLK, TPOS, and TNEG (or TDATA), and outputs it at RCLK, RPOS and RNEG (or RDATA). Inputs to the transmitter are still transmitted on TTIP and TRING, unless TAOS has been selected in which case, AMIcoded continuous ones are transmitted at the TCLK frequency. The receiver RTIP and RRING inputs are ignored when local loopback is in effect. The jitter attenuator is not in the local loop back path. Remote Loopback Remote loopback is selected by taking RLOOP, pin 26, high or by setting the RLOOP register bit via the serial interface. In remote loopback, the recovered clock and data input on RTIP and RRING are sent through the jitter attenuator and back out on the line via TTIP and TRING. Selecting remote loopback overrides any TAOS request (see Table 7). The recovered
RLOOP TAOS Input Input Signal Signal 0 0 1 0 1 X Source of Data for TTIP & TRING TDATA all 1s RTIP & RRING Source of Clock for TTIP & TRING TCLK TCLK RTIP & RRING (RCLK)
incoming signals are also sent to RCLK, RPOS and RNEG (or RDATA). A remote loopback occurs in response to RLOOP going high. Simultaneous selection of local and remote loopback modes is not valid (see Reset). In the Extended Hardware Mode the transmitted data is looped before the AMI/B8ZS/HDB3 encoder/decoder during remote loopback so that the transmitted signal matches the received signal, even in the presence of received bipolar violations. Data output on RDATA is decoded, however, if RCODE is low. Driver Performance Monitor To aid in early detection and easy isolation of non-functioning links, the IC is able to monitor transmit drive performance and report when the driver is no longer operational. This feature can be used to monitor either the device's performance or the performance of a neighboring driver. The driver performance monitor indicator is normally low, and goes high upon detecting a driver failure. The driver performance monitor consists of an activity detector that monitors the transmitted signal when MTIP is connected to TTIP and MRING is connected to TRING. DPM will go high if the absolute difference between MTIP and MRING does not transition above or below a threshold level within a time-out period. In the Host Mode, DPM is available from both the register and pin 11. Whenever more than one line interface IC resides on the same circuit board, the effectiveness of the driver performance monitor can be maximized by having each IC monitor performance of a neighboring IC, rather than having it monitor its own performance.
Notes: 1. X = Don't Care. The identified All Ones Select input is ignored when the indicated loopback is in effect. 2. Logic 1 indicates that Loopback or All Ones option is selected.
Table 7. Interaction of RLOOP with TAOS
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CS61305A
LEN 2/1/0 000 010-111 HDB3 B8ZS Encoder Encoder AMI Encoder HDB3 Decoder B8ZS Decoder
Power On Reset / Reset Upon power-up, the IC is held in a static state until the supply crosses a threshold of approximately 3 Volts. When this threshold is crossed, the device will delay for about 10 ms to allow the power supply to reach operating voltage. After this delay, calibration of the delay lines used in the transmit and receive sections commences. The delay lines can be calibrated only if a reference clock is present. The reference clock for the receiver is provided by ACLKI, or the crystal oscillator. The reference clock for the transmitter is provided by TCLK. The initial calibration should take less than 20 ms. In operation, the delay lines are continuously calibrated, making the performance of the device independent of power supply or temperature variations. The continuous calibration function eliminates any requirement to reset the line interface when in operation. However, a reset function is available which will clear all registers. In the Hardware and Extended Hardware Modes, a reset request is made by simultaneously setting both the RLOOP and LLOOP pins high for at least 200 ns. Reset will initiate on the falling edge of the reset request (falling edge of RLOOP and LLOOP). In the Host Mode, a reset is initiated by simultaneously writing RLOOP and LLOOP to the register. In either mode, a reset will set all registers to 0 and force the oscillator to its center frequency before initiating calibration. A reset will also set LOS high. Serial Interface In the Host Mode, pins 23 through 28 serve as a microprocessor/microcontroller interface. One on-board register can be written to via the SDI pin or read from via the SDO pin at the clock rate determined by SCLK. Through this register, a
TCODE (Transmit Encoder Selection) RCODE (Receiver Decoder Selection)
LOW HIGH LOW HIGH
AMI Decoder
Table 8. Encoder/Decoder Selection
Alarm Indication Signal In the Extended Hardware Mode, the receiver sets the output pin AIS high when unframed all-ones condition (blue alarm) is detected using the criteria of less than 3 zeros out of 2048 bit periods. Line Code Encoder/Decoder In the Extended Hardware Mode, three line codes are available: AMI, B8ZS and HDB3. The input to the encoder is TDATA. The outputs from the decoder are RDATA and BPV (Bipolar Violation Strobe). The encoder and decoder are selected using the LEN2, LEN1, LEN0, TCODE and RCODE pins as shown in Table 8. Parallel Chip Select In the Extended Hardware Mode, PCS can be used to gate the digital control inputs: TCODE, RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP and TAOS. Inputs are accepted on these pins only when PCS is low and will immediately change the operating state of the device. Therefore, when cycling PCS to update the operating state, the digital control inputs should be stable for the entire PCS low period. The digital control inputs are ignored when PCS is high.
16
DS157PP3
CS61305A
CS SCLK SDI SDO
R/W
0
0
0
0
1
0
X
D0 D0
D1 D1
Address/Command Byte
D2 D3 D4 D5 Data Input/Output D2 D3 D4 D5
D6 D6
D7 D7
Figure 13. Input/Output Timing
host controller can be used to control operational characteristics and monitor device status. The serial port read/write timing is independent of the system transmit and receive timing. Data transfers are initiated by taking the chip select input, CS, low (CS must initially be high). Address and input data bits are clocked in on the rising edge of SCLK. The clock edge on which output data is stable and valid is determined by CLKE as shown in Table 5. Data transfers are terminated by setting CS high. CS may go high no sooner than 50 ns after the rising edge of the SCLK cycle corresponding to the last write bit. For a serial data read, CS may go high any time to terminate the output. Figure 13 shows the timing relationships for data transfers when CLKE = 1. When CLKE = 1, data bit D7 is held until the falling edge of the 16th clock cycle. When CLKE = 0, data bit D7 is held until the rising edge of the 17th clock cycle. SDO goes to the high impedance state when the serial port is being written (R/W = 0), or if CS goes high, or at the end of the hold period of data bit D7. An address/command byte, shown in Table 9, precedes the data byte. The first bit of the address/command byte determines whether a read or a write is requested. The next six bits contain the address. The line interface responds to address 16 (0010000). The last bit is ignored.
Bit
0 1 2 3 4 5 6 7 Note:
Designation
R/W ADD0 ADD1 ADD2 ADD3 ADD4 X
Description
Read/Write Select; 0 = write, 1 = read LSB of address, Must be 0 Must be 0 Must be 0 Must be 0 Must be 1 Reserved - Must be 0 Don't Care
Bit 0 is the first bit input (LSB).
Table 9. Address/Command Byte
During a write cycle (R/W = 0), data is written to the input data register on the eight clock cycles immediately following the address/command byte. The input data format over SDI is shown in Table 10.
Bit
D0 D1 D2 D3 D4 D5 D6 D7 Note:
Designation
clr LOS clr DPM LEN0 LEN1 LEN2 RLOOP LLOOP TAOS
Description
Clear Loss of Signal Clear Driver Performance Monitor Bit 0 - Line Length Select Bit 1 - Line Length Select Bit 2 - Line Lenght Select Remote Loopback Local Loopback Transmit All Ones Select
Bit D0 is the first bit input (LSB).
Table 10. Input Data Register
Bits D0 and D1 are used to clear an interrupt issued from the INT pin, which occurs in response to a loss of signal or a problem with the output driver. Writing a "1" to either "Clear LOS" or "Clear DPM" over the serial interface has three effects:
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CS61305A
1) The current interrupt on the serial interface will be cleared. (Note that simply reading the register bits will not clear the interrupt). 2) Output data bits D5, D6 and D7 will be reset as appropriate. 3) Future interrupts for the corresponding LOS or DPM will be prevented from occurring. Writing a "0" to either "Clear LOS" or "Clear DPM" enables the corresponding interrupt for LOS or DPM.
Bit
D0 D1 D2 D3 D4
Bits D5 D6 D7 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1
Status
Reset has occurred or no program input. TAOS in effect. LLOOP in effect. TAOS/LLOOP in effect. RLOOP in effect DPM changed state since last "clear DPM" occured. 1 1 0 LOS changed state since last "clear LOS" occured. 1 1 1 LOS and DPM have changed state since last "clear LOS" and "clear DPM". Table 12. Output Data Register (bits D5-D7)
Designation
LOS DPM LEN0 LEN1 LEN2
Description
Loss of Signal Driver Performance Monitor Bit 0 - Line Length Select Bit 1 - Line Length Select Bit 2 - Line Lenght Select
respective grounds. TV+ must not exceed RV+ by more than 0.3V. Decoupling and filtering of the power supplies is crucial for the proper operation of the analog circuits in both the transmit and receive paths. A 1.0 F capacitor should be connected between TV+ and TGND, and a 0.1 F capacitor should be connected between RV+ and RGND. Use mylar or ceramic capacitors and place them as closely as possible to their respective power supply pins. A 68 F tantalum capacitor should be added close to the RV+/RGND supply. Wire-wrap breadboarding of the line interface is not recommended because lead resistance and inductance serve to defeat the function of the decoupling capacitors.
Note: Bit D0 is the first bit output (LSB)
Table 11. Output Data Register (bits D0-D4)
During a read cycle (R/W = 1), data is read from the output data register on the eight clock cycles immediately following the address/ command byte. The output data format over SDO is shown in Tables 11 and 12. Bits D2, D3 and D4 can be read to verify line length selection. Bits D5, D6 and D7 must be decoded according to Table 12. Codes 101, 110 and 111 (Bits D5, D6 and D7) indicate intermittent losses of signal and/or driver problems. The SDO pin goes to a high impedance state when not in use. The SDO and SDI pins may be tied together in applications where the host processor has a bi-directional I/O port. Power Supply The device operates from a single +5 Volt supply. Separate pins for transmit (TV+, TGND) and receive (RV+, RGND) supplies provide internal isolation. These pins should be connected externally near the device and decoupled to their
18
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DS157PP3
CS61305A
PIN DESCRIPTIONS Extended Hardware Hardware/Host
ACLKI TCLK TPOS TNEG MODE RNEG RPOS RCLK XTALIN XTALOUT DPM LOS TTIP TGND
1 2 3 4
Hardware
28 27 26 25
Extended Hardware
Host
CLKE SCLK CS SDO SDI INT
TDATA TCODE BPV RDATA
5
6 7 8
top view
24
DIP 23
22 21
9
10 11 12 13 14
20
19 18 17 16 15
AIS
TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP MRING MTIP TRING TV+
PCS RCODE
Extended Hardware
Hardware/Host
ACLKI TCLK
Hardware
Extended Hardware
Host
TAOS LLOOP RLOOP LEN2
5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 1 28 27 26 25 24
CLKE SCLK CS SDO SDI INT
TDATA TCODE
TPOS TNEG MODE
BPV RDATA
RNEG RPOS RCLK XTALIN XTALOUT
LEN1 LEN0 RGND RV+ RRING RTIP MRING MTIP TRING TV+ PCS RCODE
PLCC
top view
23 22 21 20 19
AIS
DPM LOS TTIP TGND
DS157PP3
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CS61305A
Power Supplies RGND - Ground, Pin 22. Power supply ground for all subcircuits except the transmit driver; typically 0 Volts. RV+ - Power Supply, Pin 21. Power supply for all subcircuits except the transmit driver; typically +5 Volts. TGND - Ground, Transmit Driver, Pin 14. Power supply ground for the transmit driver; typically 0 Volts. TV+ - Power Supply, Transmit Driver, Pin 15. Power supply for the transmit driver; typically +5 Volts. TV+ must not exceed RV+ by more than 0.3 V. Oscillator XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10. A 6.176 MHz (T1 operation) or 8.192 MHz (E1 operation) crystal should be connected across these pins. Overdriving the oscillator with an external clock is not supported. Control ACLKI - Alternate External Clock Input, Pin 1. A 1.544 MHz or 2.048 MHz clock signal may be input on ACLKI to calibrate the clock recovery circuit and control the transmit clock during TAOS. If a clock is not provided on ACLKI, this input must be grounded, and the oscillator in the jitter attenuator is used to calibrate the clock recovery circuit and TAOS is not available. ACLKI may not be provided by RCLK. CLKE - Clock Edge, Pin 28. (Host Mode) Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of SCLK. CS - Chip Select, Pin 26. (Host Mode) This pin must transition from high to low to read or write the serial port. INT - Receive Alarm Interrupt, Pin 23. (Host Mode) Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing "clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the power supply through a resistor (47k - 100k).
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DS157PP3
CS61305A
LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended Hardware Modes) Determines the shape and amplitude of the transmitted pulse to accommodate several cable types and lengths. See Table 3 for information on line length selection. These pins also control the receiver slicing level. LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes) Setting LLOOP to a logic 1 routes the transmit clock and data through to the receive clock and data pins. TPOS/TNEG (or TDATA) are still transmitted unless overridden by a TAOS request. Inputs on RTIP and RRING are ignored during LLOOP. The jitter attenuator is bypassed. Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset. MODE - Mode Select, Pin 5. Driving the MODE pin high places the line interface in the Host Mode. In the Host mode, a serial control port is used to control the line interface and determine its status. Grounding the MODE pin places the line interface in the Hardware Mode, where configuration and status are controlled by discrete pins. Floating the MODE pin or driving it to +2.5 V places the device in Extended Hardware Mode, where configuration and status are controlled by discrete pins. When floating MODE, there should be no external load on the pin. MODE defines the status of 13 pins (see Table 2). PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode) Setting PCS low causes the line interface to accept the TCODE, RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP and TAOS inputs. RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode) Setting RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting RCODE high enables the AMI receiver decoder (see Table 8). RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes) Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter attenuator and through the driver back to the line. The recovered signal is also sent to RCLK and RPOS/RNEG (or RDATA). Any TAOS request is ignored. Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset. SCLK - Serial Clock, Pin 27. (Host Mode) Clock used to read or write the serial port registers. SCLK can be either high or low when the line interface is selected using the CS pin. SDI - Serial Data Input, Pin 24. (Host Mode) Input for the input data register. Sampled on the rising edge of SCLK.
DS157PP3
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CS61305A
SDO - Serial Data Output, Pin 25. (Host Mode) Status and control output from the output data register. If CLKE is high SDO is valid on the rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to a high-impedance state when the serial port is being written, or if CS is high, or after bit D7 is output. TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes) Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined by ACLKI. TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode) Setting TCODE low enables B8ZS or HDB3 zero substitution in the transmitter encoder. Setting TCODE high enables the AMI transmitter encoder . Data RCLK - Recovered Clock, Pin 8. The receiver recovered clock is output on this pin. RDATA - Receive Data - Pin 7. (Extended Hardware Mode) Data recovered from the RTIP and RRING inputs is output in NRZ format at this pin, after being decoded by the line code decoder. RDATA is stable and valid on the falling edge of RCLK. RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and Host Modes) The receiver recovered NRZ digital data from RTIP and RRING is output on these pins. A positive pulse (with respect to ground) received on the RTIP pin generates a logic 1 on RPOS, and a positive pulse (with respect to ground) received on the RRING pin generates a logic 1 on RNEG. In the Hardware Mode, RPOS and RNEG are stable and valid on the rising edge of RCLK. In the Host Mode, CLKE determines the clock edge for which RPOS and RNEG are stable and valid (see Table 5). RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20. The AMI receive signal is input on these pins. A center-tapped, center-grounded, 2:1, step-up transformer is required on these inputs, as shown in Figure A1 of the Applications section. Clock and data are recovered and output on RCLK and RPOS/RNEG or RDATA. TCLK - Transmit Clock, Pin 2. The1.544 MHz (T1 operation) or 2.048 MHz (E1 operation) transmit clock is input on this pin. TPOS/TNEG or TDATA are sampled on the falling edge of TCLK. TDATA - Transmit Data, Pin 3. (Extended Hardware Mode) Data to be transmitted by the TTIP and TRING outputs is input in NRZ format at this pin, after being encoded by the line code encoder. TDATA is sampled on the falling edge of TCLK.
22
DS157PP3
CS61305A
TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and Host Modes) The transmit NRZ digital data to TTIP and TRING is input on these pins. A logic 1 on TPOS causes a positive pulse (with respect to ground) to be transmitted on the TTIP pin, and a logic 1 on TNEG causes a negative pulse (with respect to ground) to be transmitted on the TRING pin. TPOS and TNEG are sampled on the falling edge of TCLK. TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16. The AMI signal is driven to the line through these pins. This output is designed to drive a 75 load. A transformer is required as shown in Figure A1 of the Applications section. Clock and data are sourced on TCLK and TPOS/ TNEG or TDATA. Status AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode) AIS goes high when unframed all-ones condition (blue alarm) is detected, using the detection criteria of less than three zeros out of 2048 bit periods. BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode) BPV strobes high when a bipolar violation is detected in the received signal. B8ZS (or HDB3) zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been enabled. DPM - Driver Performance Monitor, Pin 11. (Hardware and Host Modes) DPM goes high if no activity is detected on MTIP and MRING. LOS - Loss of Signal, Pin 12. LOS goes high when 175 consecutive zeros have been received. LOS returns low when 3 ones are received within 32 bit periods containing no more than 15 consecutive zeros. MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes) These pins are normally connected to TTIP and TRING and monitor the transmitter output. If the INT pin in the Host mode is used, and the monitor is not used, writing a "1" to the "clear DPM" bit will prevent an interrupt from the driver performance monitor.
DS157PP3
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CS61305A
28
15 E1
1
14
28 pin Plastic DIP
D A A1 B1 e1 B L
SEATING PLANE
C eA
DIM A A1 B B1 C D E1 e1 eA L
NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
MILLIMETERS MIN NOM MAX 3.94 4.32 5.08 0.51 0.76 1.02 0.36 0.46 0.56 1.02 1.27 1.65 0.20 0.25 0.38 36.45 36.83 37.21 13.72 13.97 14.22 2.41 2.54 2.67 15.87 15.24 3.18 3.81 0 15
MIN 0.155 0.020 0.014 0.040 0.008 1.435 0.540 0.095 0.600 0.125 0
INCHES NOM 0.170 0.030 0.018 0.050 0.010 1.450 0.550 0.100 -
MAX 0.200 0.040 0.022 0.065 0.015 1.465 0.560 0.105 0.625 0.150 15
28-pin PLCC
28
E1 E
MILLIMETERS INCHES
DIM A A1 B D/E
D1
MIN 4.20 2.29 0.33
NOM 4.45 2.79 0.41
MAX 4.57 3.04 0.53
MIN
NOM
MAX
0.165 0.175 0.180 0.090 0.110 0.120 0.013 0.016 0.021
12.32 12.45 9.91 1.19 10.41 1.27
12.57 0.485 0.490 0.495 11.58 0.450 0.453 0.456 10.92 0.390 0.410 0.430 1.35 0.047 0.050 0.053
D1/E1 11.43 11.51 D2/E2 e
D
B D2/E2
e A1 A
24
DS157PP3
CS61305A
APPLICATIONS
RTIP
19 R1 20 R2
1 3 5 2CT:1
2 RECEIVE LINE 6
RRING CS61305A TRING
16
0.47 F R3
2
1 TRANSMIT LINE
TTIP
13
R4
6 T1
5
Figure A1. Line Interface Circuitry
Frequency MHz
Crystal XTL
Cable 100
R1 and R2 200
LEN2/1/0
T1 turns ratio 1:1.15 1:2 1:2.3 1:1.26 1:2 1:1 1:2 1:1 1:2 1:1 1:2
R3 and R4 0 9.4 9.4 0 8.7 0 15 0 9.4 10 14.3
1.544 (T1) CXT6176
0/1/1 - 1/1/1
2.048 (E1) CXT8192
120
240
75
150
0/0/0 0/0/0 0/0/1 0/0/1 0/0/0 0/0/0 0/0/1 0/0/1
Typical TX Return Loss (dB) 0.5 20 28 0.5 12 0.5 30 0.5 24 5 12
Note: Refer to Table A3 for specific transformer recommendations.
Table A1. External Component Values
Line Interface Figure A1 illustrates the external components for the line interface circuitry and Table A1 shows the specific components for each application. Figures A2-A4 show typical T1 and E1 line interface application circuits. Figure A2 illustrates a T1 interface in the Host Mode. Figure A3 illustrates a 120 E1 interface in the Hardware
DS157PP3
Mode. Figure A4 illustrates a 75 E1 interface in the Extended Hardware Mode. The receiver transformer has a grounded center tap on the IC side. Resistors between the RTIP and RRING pins to ground provide the termination for the receive line.
25
CS61305A
+5V + 68 F RGND 28 Control & Monitor 1 12 11 RV+ 5 7 6 Frame Format Encoder/ Decoder 8 3 4 2 9 XTL 10 MODE RPOS RNEG RCLK
TPOS
0.1 F 21 RV+ 15 TV+
+
1.0 F TGND
+5V 100 k
CLKE ACLKI
LOS
SCLK CS
INT
27 26 23 24 25 P Serial Port
DPM
SDI SDO
CS61305A IN HOST MODE
RTIP
19 200 20 17 18 16 13 0.47 F 200
1 2 3 5 2CT:1 PE-65351 RECEIVE 6 LINE
RRING
MTIP
TNEG TCLK
XTALIN XTALOUT RGND 22 TGND 14
MRING TRING
TTIP
2 6 1:1.15 PE-65388
1 TRANSMIT 5 LINE
Figure A2. T1 Host Mode Configuration
Figures A2-A4 show a 0.47 F capacitor in series with the transmit transformer primary. This capacitor is needed to prevent any output stage imbalance from resulting in a DC current through the transformer primary. This current might saturate the transformer producing an output offset level shift. Transformers Recommended transmitter and receiver transformer specifications are shown in Table A2. The transformers in Table A3 are recommended for use with the CS61305A. Refer to the "Telecom Transformer Selection Guide" for detailed schematics which show how to connect the line interface IC with a particular transformer.
Selecting an Oscillator Crystal Specific crystal parameters are required for proper operation of the jitter attenuator. It is recommended that the Crystal Semiconductor CXT6176 crystal be used for T1 applications and the CXT8192 crystal be used for E1 applications. Line Protection Secondary protection components can be added to provide lightning surge and AC power-cross immunity. Refer to the Application Note "Secondary Line Protection for T1 and E1 Line Cards" for detailed information on the different electrical safety standards and specific application circuit recommendations.
26
DS157PP3
CS61305A
+5V + 68 F RGND 28 1 Control & Monitor 26 27 12 11 5 7 6 Frame Format Encoder/ Decoder 8 3 4 2 9 XTL 10 TAOS ACLKI RLOOP LLOOP LOS DPM MODE RPOS RNEG RCLK TPOS TNEG TCLK XTALIN XTALOUT RGND 22 TGND 14 MTIP MRING TRING TTIP 17 18 16 13 CS61305A IN HARDWARE MODE RTIP 19 1 240 3 RRING 20 240 5 2 RECEIVE 6 LINE LEN0 LEN1 LEN2 23 24 25 Line Length Setting 0.1 F 21 RV+ 15 TV+ + 1.0 F TGND
2CT:1 PE-65351 0.47 F 2 6
1 TRANSMIT 5 LINE
1:1.26 PE-65389
Figure A3. 120 , E1 Hardware Mode Configuration
+5V + 68 F RGND 17 18 6 28 Control & Monitor 1 26 27 12 11 5 4 7 Frame Format Encoder/ Decoder 8 3 2 9 XTL 10 RCODE PCS BPV TAOS ACLKI RLOOP LLOOP LOS AIS MODE TCODE RDATA RCLK TDATA TCLK XTALIN XTALOUT RGND 22 TGND 14 TRING TTIP 16 13 CS61305A IN EXTENDED HARDWARE MODE RTIP 19 1 150 3 150 5 2 RECEIVE 6 LINE LEN0 LEN1 LEN2 23 24 25 Line Length Setting 0.1 F 21 RV+ 15 TV+ + 1.0 F TGND
RRING
20
2CT:1 PE-65351 0.47 F 2 6
3 TRANSMIT 5 LINE
1:1 PE-65389
Figure A4. 75 , E1 Extended Hardware Mode Configuration DS157PP3 27
CS61305A
Parameter Turns Ratio
Receiver 1:2 CT 5%
Transmitter 1:1 1.5 % for 75 E1 1:1.15 5 % for 100 T1 1:1.26 1.5 % for 120 E1 1.5 mH min. @ 772 kHz 0.3 H max. @ 772 kHz 0.4 H max. @ 772 kHz 18 pF max. 16 V-s min. for T1 12 V-s min. for E1
Primary Inductance Primary Leakage Inductance Secondary Leakage Inductance Interwinding Capacitance ET-constant
600 H min. @ 772 kHz 1.3 H max. @ 772 kHz 0.4 H max. @ 772 kHz 23 pF max. 16 V-s min. for T1 12 V-s min. for E1
Table A2. Transformer Specifications
Interfacing The CS61305A With the CS62180B T1 Transceiver To interface with the CS62180B, connect the devices as shown in Figure A5. In this case, the line interface and CS62180B are in Host mode controlled by a microprocessor serial interface. If the line interface is used in Hardware mode, then the line interface RCLK output must be inverted before being input to the CS62180B. If the CS61305A is used in Extended Hardware Mode, the RCLK output does not have to be inverted before being input to the CS62180B.
TO HOST CONTROLLER
SCLK SDO SDI CS
TCLK TPOS TNEG
1.544 MHz CLOCK SIGNAL
ACLK TCLK TPOS TNEG
SCLK SDO SDI CS INT 22k V+ 100k V+
RNEG RPOS RCLK
RNEG RPOS RCLK
CLKE MODE
CS62180B
CS61305A
Figure A5. Interfacing the CS61305A with a CS62180B (Host Mode)
28
DS157PP3
CS61305A
Application RX: T1 & E1 TX: T1 TX: E1 (75 & 120 ) RX &TX: T1 RX &TX: E1 (75 & 120 ) RX &TX: T1 RX &TX: E1 (75 & 120 ) RX : T1 & E1 TX: E1 (75 & 120 )
Turns Ratio(s) 1:2CT
Manufacturer Pulse Engineering Schott Bel Fuse Pulse Engineering Schott Bel Fuse Pulse Engineering Schott Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering Pulse Engineering
Part Number PE-65351 67129300 0553-0013-HC PE-65388 67129310 0553-0013-RC PE-65389 67129320 0553-0013-SC PE-65565 0553-0013-7J PE-65566 0553-0013-8J PE-65765 S553-0013-06 PE-65766 S553-0013-07 PE-65835 PE-65839
Package Type 1.5 kV through-hole, single
1:1.15
1.5 kV through-hole, single
1:1.26 1:1 1:2CT 1:1.15 1:2CT 1:1.26 1:1 1:2CT 1:1.15 1:2CT 1:1.26 1:1 1:2CT 1:1.26 1:1
1.5 kV through-hole, single
1.5 kV through-hole, dual 1.5 kV through-hole, dual
1.5 kVsurface-mount, dual 1.5 kV surface-mount, dual
3 kV through-hole, single EN60950, EN41003 approved 3 kV through-hole, single EN60950, EN41003 approved
Table A3. Recommended Transformers
DS157PP3
29
* Notes *
CDB61534, CDB61535, CDB61535A, CDB6158, CDB6158A, CDB61574, CDB61574A, CDB61575, CDB61577, CDB615304A, & CDB61305A
Line Interface Evaluation Board
Features General Description
The evaluation board includes a socketed line interface device and all support components necessary for evaluation. The board is powered by an external 5 Volt supply. The board may be configured for 100 twisted-pair T1, 75 coax E1, or 120 twisted-pair E1 operation. Binding posts are provided for line connections. Several BNC connectors are available to provide system clocks and data I/O. Two LED indicators monitor device alarm conditions. The board supports all line interface operating modes. ORDERING INFORMATION: CDB61534, CDB61535. CDB61535A, CDB6158, CDB6158A, CDB61574, CDB61574A, CDB61575, CDB61577, CDB61304A, CDB61305A
+5V 0V
* * All Required Components for Complete
Socketed Line Interface Device Line Interface Evaluation Interface
* Configuration by DIP Switch or Serial * LED Status Indicators for Alarm Conditions * Support for Host, Hardware, and
Extended Hardware Modes
Mode Select Circuit Reset Circuit Serial Interface Control Circuit Hardware Control Circuit LED Status Indicators ACLKI TCLK TPOS (TDATA) TNEG (TCODE) RCLK RPOS (RDATA) RNEG (BPV)
TTIP
TRING
CS61534, CS61535, CS61535A, CS6158, CS6158A, CS61574, CS61574A, CS61575, CS61577, CS61304A or CS61305A
RTIP
RRING
XTL
Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581
SEP '95 DS40DB3 31
LINE INTERFACE EVALUATION BOARD
POWER SUPPLY As shown on the evaluation board schematic in Figure 1, power is supplied to the evaluation board from an external +5 Volt supply connected to the two binding posts labeled +5V and GND. Transient suppressor D10 protects the components on the board from over-voltage damage and reversed supply connections. The recommended power supply decoupling is provided by C1, C2 and C3. Ceramic capacitor C1 and electrolytic capacitor C2 are used to decouple RV+ to RGND. Capacitor C3 decouples TV+ to TGND. The TV+ and RV+ power supply traces are connected at the device socket U1. A ground plane on the component side of the evaluation board insures optimum performance. BOARD CONFIGURATION Pins on line interface device U1 with more than one pin name have different functions depending on the operating mode selected. Pin names not enclosed in parenthesis or square brackets describe the Hardware mode pin function. Pin names enclosed in parenthesis describe the Extended Hardware mode pin function. Pin names enclosed in square brackets describe the Host mode pin function.
Table 1 explains how to configure the evaluation board jumpers depending on the device installed and the desired operating mode. Mode selection is accomplished with slide switch SW1 and jumpers JP2, JP6, and JP7. The CS61535A, CS61574A, CS61575, CS61577, CS61304A, and CS61305A support the Hardware, Extended Hardware, and Host operating modes. The CS61534, CS61535, and CS61574 support the Hardware and Host operating modes. The CS6158 and CS6158A only support the Hardware operating mode. Hardware Mode In the Hardware operating mode, the line interface is configured using DIP switch S2. The digital control inputs to the device selected by S2 include: transmit all ones (TAOS), local loopback (LLOOP), remote loopback (RLOOP), and transmit line length selection (LEN2,LEN1,LEN0). Closing a DIP switch on S2 towards the label sets the device control pin of the same name to logic 1 (+5 Volts). Note that S2 switch positions TCODE and RCODE have no function in Hardware mode. In addition, the host processor interface connector JP1 should not be used in the Hardware mode. Two LED status indicators are provided in Hardware mode. The LED labeled DPM (AIS) illuminates when the line interface asserts the Driver
JUMPER JP1 JP2, JP6, JP7 JP3 JP4 JP5 JP8
POSITION A-A B-B IN OUT C-C D-D E-E F-F IN OUT
FUNCTION SELECTED Connector for external processor in Host operating mode. Extended Hardware operating mode. Hardware or Host operating modes. Hardware or Extended Hardware operating modes. Host operating mode. Connects the ACLKI BNC input to pin 1 of device. Grounds the ACLKI BNC input through 51 resistor R1. Transmit line connection for all applications except those listed for "F-F" on the next line. 75 coax E1 applications using the Schott 12932/12532 or PE-65389/65566 at transformer T1. Shorts resistor R2 for all applications except those listed for "OUT" on the next line. Inserts resistor R2 for 75 coax E1 applications using the CS61534, 35, 58, 74, or 77.
Table 1. Evaluation Board Jumper Settings
32
DS40DB3
LINE INTERFACE EVALUATION BOARD
RV+ +5V D10 P6KE GND (0V) C2 0.1mF C3 1m F 15 TV+ Pin 6 RNEG (BPV) RCLK TCLK
TCLK
RV+
C1 68mF + RV+ 22 RGND 21 RV+ 9
Prototyping Area
14 TGND
R13 (only included for CS6158/58A) 1kW E1: CXT8192 T1: CXT6176 (not included for CS6158/58A) RTIP 19 R10 200W Change R9 and R10 for E1 operation T2 (see Table 2) 2:1 RTIP
6 RNEG (BPV) 8 RCLK 2 TCLK 3 TPOS (TDATA) 7 RPOS (RDATA)
RCLK
XTALIN {CS6158/58A: RT} XTALOUT {CS6158/58A: NC} RTIP
10
TPOS (TDATA) RPOS (RDATA) RV+ R15 100
S2
Pin 3 Pin 7 ACLKI R1 51.1 D JP4 D
U1
1
ACLKI TNEG B A RCODE TCODE LEN0/INT LEN1/SDI LEN2/SD0 RLOOP/CS LLOOP/SCLK TAOS/CLKE INT SDI SDO CS SCLK JP1 D9 1N914 D8 JP2
C B A
C Pin 4
ACLKI TNEG (TCODE) RRING TTIP MRING (PCS)
RRING 20 TTIP 13 Pin 18 18 B
R9 200W RRING
4
JP6
B A 0.47 m F C5 E JP5 TTIP E
23 LEN0 [INT] 24 LEN1 [SDI] 25 LEN2 [SD0] 26 RLOOP [CS] 27 LLOOP [SCLK] 28 TAOS [CKLE]
TRING A TRING MTIP (RCODE) 16 Pin 17 17 B A JP7 B A
JP8
FF T1 (see Table 2) TRING
R2 4.4W LOS 12 DPM RV+ (AIS) Q2 2N2222 LED D2 R5 470 RV+ LOS Q1 2N2222 LED D3 R6 470 U1: CS61534, CS61535, CS61535A, CS6158, CS6158A, CS61574, CS61574A, CS61575, CS61577, CS61304A, OR CS61305A (Used only for E1 75W applications with the CS61534, CS61535, CS6158, CS61574, OR CS61577)
JP3
MODE DPM (AIS) 5 R14 4.7kW SIP 11
S1 RESET R4 221kW
C4 0.047m F 6 3
MODE MODE SW1
8
7 RV+
5 R16 1k
1
2
4 HOST:3-1,6-8 EXT HW: 3-2, 6-7 HW: 3-4, 6-5
R18 R17 10k W 10k W
Figure 1. Evaluation Board Schematic
DS40DB3
33
LINE INTERFACE EVALUATION BOARD
Performance Monitor alarm. The LED labeled LOS illuminates when the line interface receiver has detected a loss of signal. Extended Hardware Mode In the Extended Hardware operating mode, the line interface is configured using DIP switch S2. The digital control inputs to the device selected by S2 include: transmit all ones (TAOS), local loopback (LLOOP), remote loopback (RLOOP), transmit line length selection (LEN2, LEN1, LEN0), transmit line code (TCODE), and receive line code (RCODE). Closing a DIP switch (moving it towards the S2 label) sets the device control pin of the same name to logic 1 (+5 Volts). Note that the TCODE and RCODE options are active low and are enabled when the switch is moved away from the S2 label. The parallel chip select input PCS is tied to ground in Extended Hardware mode to enable the device to be reconfigured when S2 is changed. In addition, the host processor interface connector JP1 should not be used in Extended Hardware mode. Two LED status indicators are provided in Extended Hardware mode. The LED labeled DPM (AIS) illuminates when the line interface detects the receive blue alarm (AIS). The LED labeled LOS illuminates when the line interface receiver has detected a loss of signal. Host Mode In the Host operating mode, the line interface is configured using a host processor connected to the serial interface port JP1. The S2 switch position labeled CLKE selects the active edge of SCLK and RCLK. Closing the CLKE switch selects RPOS and RNEG to be valid on the falling edge of RCLK and SDO to be valid on the rising edge of SCLK as required by the CS2180B T1 framer. All other DIP switch positions on S2 should be open (logic 0) to prevent shorting of the serial in34
terface signals. Resistor R15 is a current limiting resistor that prevents the serial interface signals from being shorted directly to the +5 Volt supply if any S2 switch, other than CLKE, is closed. Jumper JP3 should be out so the INT pin may be externally pulled-up at the host processor interrupt pin. Two LED status indicators are provided in Host mode. The LED labeled DPM (AIS) illuminates when the line interface asserts the Driver Performance Monitor alarm. The LED labeled LOS illuminates when the line interface receiver has detected a loss of signal. Manual Reset A manual reset circuit is provided that can be used in Hardware and Extended Hardware modes. The reset circuit consists of S1, R4, R16, C4, D8, and D9. Pressing switch S1 forces both LLOOP and RLOOP to a logic 1 and causes a reset. A reset is only necessary for the CS61534 device to calibrate the center frequency of the receiver clock recovery circuit. All other line interface units use a continuously calibrated clock recovery circuit that eliminates the reset requirement. TRANSMIT CIRCUIT The transmit clock and data signals are supplied on BNC inputs labeled TCLK, TPOS(TDATA), and TNEG. In the Hardware and Host operating modes, data is supplied on the TPOS(TDATA) and TNEG connectors in dual NRZ format. In the Extended Hardware operating mode, data is supplied in NRZ format on the TPOS(TDATA) connector and TNEG is not used. The transmitter output is transformer coupled to the line through a transformer denoted as T1 in Figure 1. The signal is available at the TTIP and TRING binding posts. Capacitor C5 is the recommended 0.47 F DC blocking capacitor.
DS40DB3
LINE INTERFACE EVALUATION BOARD
The evaluation board supports 100 twisted-pair T1, 75 coax E1, and 120 twisted-pair E1 operation. The CDB61534, CDB61535, CDB6158, CDB61574, and CDB61577 are supplied from the factory with a 1:2 transmit transformer that may be used for all T1 and E1 applications. The CDB61 53 5A, CDB61 58A, CDB61574A, CDB61575, CDB61304A, and CDB61305A are supplied with a 1:1.15 transmit transformer installed for T1 applications. An additional 1:1:1.26 transformer for E1 applications is provided with the board. This transformer requires JP5 to be jumpered across F-F for 75 coax E1 applications. The CDB6 15 34 , CDB6 15 35 , CDB6158, CDB61574, and CDB61577 require the JP8 jumper to be out for 75 coax E1 applications. This inserts resistor R2 to reduce the transmit pulse amplitude and meet the 2.37 V nominal pulse amplitude requirement in CCITT G.703. In addition, R2 increases the equivalent load impedance across TTIP and TRING. RECEIVE CIRCUIT The receive line interface signal is input at the RTIP and RRING binding posts. The receive signal is transformer coupled to the line interface device through a center-tapped 1:2 transformer. The transformer produces ground referenced pulses of equal amplitude and opposite polarity on RTIP and RRING. The receive line interface is terminated by resistors R9 and R10. The evaluation boards are supplied from the factory with 200 resistors for terminating 100 T1 twisted-pair lines. Resistors R9 and R10 should be replaced with 240 resistors for terminating 120 E1 twisted-pair lines or 150 resistors for terminating 75 E1 coaxial lines. Two 243 resistors and two 150 resistors are included with the evaluation board for this purpose.
DS40DB3
The recovered clock and data signals are available on BNC outputs labeled RCLK, RPOS(RDATA), and RNEG(BPV). In the Hardware and Host operating modes, data is output on the RPOS(RDATA) and RNEG(BPV) connectors in dual NRZ format. In the Extended Hardware operating mode, data is output in NRZ format on the RPOS(RDATA) connector and bipolar violations are reported on the RNEG(BPV) connector. QUARTZ CRYSTAL A quartz crystal must be installed in socket Y1 for all devices except the CS6158 and CS6158A. A Crystal Semiconductor CXT6176 crystal is recommended for T1 operation and a CXT8192 is recommended for E1 operation. The evaluation board has a CXT6176 installed at the factory and a CXT8192 is also provided with the board. The CDB6158 and CDB6158A have resistor R13 installed instead of a crystal. This connects the RT pin of the device to the +5 Volt supply. ALTERNATE CLOCK INPUT The ACLKI BNC input provides the alternate clock reference for the line interface device (ACLK for the CS61534) when JP4 is jumpered across C-C. This clock is required for the CS61534, CS61535, CS6158, and CS6158A operation but is optional for all other line interface devices. If ACLKI is provided, it may be desirable to connect both C-C and D-D positions on JP4 to terminate the external clock source providing ACLKI with the 51 resistor R1. If ACLKI is optional and not used, connector JP4 should be jumpered across D-D to ground pin 1 of the device through resistor R1. TRANSFORMER SELECTION To permit the evaluation of other transformers, Table 2 lists the transformer and line interface device combinations that can be used in T1 and E1
35
LINE INTERFACE EVALUATION BOARD
applications. A letter at the intersection of a row and column in Table 2 indicates that the selected transformer is supported for use with the device. The transformer is installed in the evaluation board with pin 1 positioned to match the letter illustrated on the drawing in Table 2. For example, the Pulse Engineering PE-65388 transformer may be used with the transmitter of the CS61575 device for 100 T1 applications only (as indicated by note 3) when installed in transformer socket T1 with pin 1 at position D (upper right). PROTOTYPING AREA A prototyping area with power supply and ground connections is provided on the evaluation board. This area can be used to develop and test a variety of additional circuits like a data pattern generator, CS2180B framer, system synchronizer PLL, or specialized interface logic. EVALUATION HINTS 1. Properly terminate TTIP/TRING when evaluating the transmit output signal. For more information concerning pulse shape evaluation, refer to the Crystal application note entitled "Measurement and Evaluation of Pulse Shapes in T1/E1 Transmission Systems." 2. Change the receiver terminating resistors R9 and R10 when evaluating E1 applications. Resistors R9 and R10 should be replaced with 240 resistors for terminating 120 E1 twisted-pair lines or 150 resistors for terminating 75 E1 coaxial lines. Two 243 resistors and two 150 resistors are included with the evaluation board for this purpose. 3. Closing a DIP switch on S2 towards the label sets the device control pin of the same name to logic 1 (+5 Volts).
4. To avoid damage to the external host controller connected to JP1, all S2 switch positions (except CLKE) should be open. In the Host operating mode, the CLKE switch selects the active edge of SCLK and RCLK.
36
DS40DB3
LINE INTERFACE EVALUATION BOARD
LINE INTERFACE UNIT TRANSFORMER (Turns Ratio)1,2 PE-65351 (1:2CT) Schott 12930 (1:2CT) PE-65388 (1:1.15) Schott 12931 (1:1.15) PE-65389 (1:1:1.26) Schott 12932 (1:1:1.26) PE-64951 (dual 1:2CT) Schott 11509 (dual 1:2CT) PE-65565 (dual 1:1.15 & 1:2CT) Schott 12531 (dual 1:1.15 & 1:2CT) PE-65566 (dual 1:1:1.26 & 1:2CT) Schott 12532 (dual 1:1:1.26 & 1:2CT) '34 '35 '35A '58 '58A '74,'77 '74A '75 '304A, '305A RX TX A B D3,5 C3,5 D4,5 C4,5
RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX ADADA ADA ADA A BCBCB BCB BCB B D3 D3 D3 D3 3 3 3 C C C C3 D4 D4 D4 D4 4 4 4 C C C C4 E E E E E E E E E3 E3 E3 E3 3 3 3 E E E E3 E4 E4 E4 E4 4 4 4 E E E E4 NOTES:
E3,5 E3,5 E4,5 E4,5
T2 B
1. A letter at the intersection of a row and column in Table 2 indicates that the selected transformer is supported for use with the device. The transformer is installed in the evaluation board with pin 1 positioned to match the letter illustrated in the drawing to the left. T2 2. The receive transformer (RX) is soldered at location T2 on the evaluation board and is used for all applications. The transmit transformer (TX) is socketed at location T1 on the evaluation board and may be changed according to the application. For use in 75 and 120 E1 applications only. Place jumper JP5 in position F-F for 75 E1 applications requiring a 1:1 turns ratio.
A
D
3. For use in 100 T1 twisted-pair applications only. 4.
C T1
E T1
5. Transmitter return loss improves when using a 1:2 turns ratio transformer with the appropriate transmit resistors.
Table 2. Transformer Applications
DS40DB3
37
LINE INTERFACE EVALUATION BOARD
Figure 2. Silk Screen Layer (NOT TO SCALE)
38
DS40DB3
LINE INTERFACE EVALUATION BOARD
Figure 3. Top Ground Plane Layer (NOT TO SCALE)
DS40DB3
39
LINE INTERFACE EVALUATION BOARD
Figure 4. Bottom Trace Layer (NOT TO SCALE)
40
DS40DB3
* Notes *
* Notes *
* Notes *
Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation

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